Tooth Whitening Diagram

Exercises for Class 3 °

COMMUNICATION FOR THOSE WHO HAVE HAD THE CANCELLATION OF DEBT

eserczi choice must be made 5 for each topic proposed and delivered in the notebook without fail August 24, 2009



Logic gates






















Porte1) Give the truth table of a NAND an OR, an EXOR and a NOT

Porte2) Give the truth table of AND, NOR a, a Nexor

Porte3) suppose that an input to AND there are signals in Figure A, B design the output

Porte4) suppose that an input to an EXOR there are signals in Figure A, B design the output

Porte5) suppose that an input to AND there are signals in figure c, B draw the output

Porte6) suppose that an input to a NOR there are signals in Figure A, C, draw the output


truth tables, circuits, functions, and minimization

map1:

Draw a map, determine the simplified function and the network of the following truth tables:

The outputs are 1 to 010, 011, 110

The outputs are 1 for 0011, 0111, 1001, 1010


Mappa2:
want a keyboard with 4 keys encoder input (A, B, C, D) and three outputs (y1, y2, y3). If the button is pressed its bit is 1. If you have not pressed any button is pressed, or more than one key to all three outputs are always zero. The matches are A-001, B-010, C-100 and D-101.Dopo you draw the block diagram, mapping all three outputs while minimizing and calculating the Boolean expression. Finally, design the network of NAND only necessary to implement the desired functionality.


Mappa3:
want a keyboard encoder with 4-key input (S, A, B, C) and three outputs (y1, y2, y3). If the button is pressed its bit is 1. The key S is the schift and then must be pressed together with another key. If you have not pressed any button is pressed or the S key are pressed simultaneously alone or A and B or C, all three outputs are always zero. The matches are A-001 to-010, B-011, B-100, C-101, C-110.
After drawing the block diagram, mapping all three outputs while minimizing and then calculating the Boolean expression. Finally, design the network of NAND only necessary to implement the desired functionality.


Mappa4:
want a decoder that led pilots 4 and signals the presence of a code input. Assuming it has 4 inputs and the first LED lights with 0011, the second with 1100, the third with 1001 and the last with 000 draw a diagram Block, 4-output mapping by minimizing and then calculating the Boolean expression. Finally, design the network of NAND only necessary to implement the desired functionality.

Mappa5:
We want to design a multiplex with two channels A, B for data and a S for selection. Draw the block diagram, map the Boolean function, minimize it and draw a network of just Nand that implements the desired functionality.

Repeat for a demultiplex.


Mappa6: You want to build a network that signals the presence of a prime number, LED lights, when they are encoded on 4 bits input

Mappa7: Building a network with 3-bit input and 6 output bits which gives the square of the input binary number. Carried out only with Nand.

Mappa8: Design a circuit output signal with an LED if the input of 4 bits is a prime number or a number divisbile for 3. Carried out only with Nand.


Numbering system

Sist1:
Convert the number 24 in base 2, 5, 8, 16

Sist2:

Make the sum of the number in base 2 (AB) 16 and under (113 ) base 8

Sist3:

Make the sum by the number 8 (10001110) and the number in base 2 (1F) in base 16

Sist4:
Make a difference in base 2 of the number (13 ) under 16 and (13) in base 8

Sist5: Code the number 5 on 4-bit Gray-coded


Lab1: Describe how the pin and the circuit 74153, 7404, 7486


Circuits

NB network should be performed with only NAND and minimized

Circ1: Designing a network that complements the two 4 inputs 4 outputs on

Circ2: Designing a network that carries out the function y = 2x +1 with 4-bit input and 5-bit Output

Circ3: Designing a network that carries out the function y = 2x-3 with 3-bit input and 4 output bits (negative numbers should be in addition to 2)

Circ4: Design a network that carries function y = x ^ 2-4 with 3-bit input and 4 output bits (negative numbers should be in addition to 2)

Circ5: Designing a network that carries out the function y = x ^ 2-3x with 3 bit input and 4 output bits (negative numbers should be in addition to 2)


Latch and Flip Flop

1) Draw a RS latch using NAND gates giving its truth table

2 ) Draw the circuit capable of switching on the rising edge of a impuso place at the entrance and tell the difference between latch and flip its truth table flop.dandone

3) Draw an SR type flip flop using NAND gates giving its truth table

4) Draw a SR latch enable it to have the truth table giving his

5) Draw a D-type flip flop and give its truth table

6) Draw a T-type flip flop and give the its truth table

7) Draw a type JK flip flop and give its truth table

8) Draw a type JK flip flop master slave




















9) Assume that the input of an SR flip flop there are signals A and B draw the output (for combinations that are not allowed to put Q = 0)

10) Assume that the input of an SR flip flop there are signals C and B, draw the output (for combinations that are not allowed to put Q = 0)

11) Assume that the input of a D flip flop there is the signal A and the clock is acting on the falling edge at the time 1,2,3 ... drawing the release

12) Assume that the input of a flip flop T there is the signal B and the clock is acting on the rising edge at the time 1,2,3 ... drawing the release

13) Assume that the input of a JK flip flop there are signals A and B and the clock is acting on the falling edge at the time 1,2,3 ... drawing the release

14) Assume that the input of a JK flip flop there are signals A and C and the clock is acting on the falling edge at the time 1,2,3 ... drawing the release

15) Assume that the input of a JK flip flop there are signals A and B, the signal C is applied to the presets and the clock is acting on the falling edge at the time 1,2,3. .. drawing the release

16) Assume that the input of a JK flip flop there are signals A and B, the signal C is applied to the clock and Clea acting on the rising edge at the time 1,2,3. .. drawing the release

counters asynchronous and synchronous

1) Draw a 3-bit asynchronous counter

2) Draw a 3-bit asynchronous counter that counts up to 5

3) Draw an asynchronous counter to count up 12-

4) Draw a 3-bit synchronous counter

5) Draw a 3-bit synchronous counter that counts up to 6

7) Design a synchronous counter that counts up to 13

8) Draw the asynchronous counter studied in the laboratory describing the most important functions of his feet

9) Draw the synchronous counter studied in the laboratory by describing the most important functions of his feet


Registers

1) Draw a log and describe its function

2) Draw regsitro studied in the laboratory and describe its operation of the pin and pin the most significant.


Laboratory

1) Indicate what type of chip is the 7400, 7404, 7402, 7408, 7432 and 7486 and give the pinout

2) Indicate what type of chip is the 74153, 74154 and give the pinout.

3) Indicate what type of chip is the 9368 and give the pinout.

4) indicates that type of integration is the 7474, 74112 and give the pinout.

5) indicates that type of integration is the LS93, 74190 and give the pinout.

6) Indicate what type of chip is the 74194 and give the pinout.

8) Give the definition of rise time, fall time and duration of a pulse

Hotfilebig Butt Bootyblog

exercises for class 4 th

FOR ALL THOSE THAT DO NOT EXCEED THE FORM:

should be performed at least 5 exercises for each topic
















NOTE: If not stated explicitly component values \u200b\u200bare indicated by the value of their subscript.



Continue


Fig.1: Knowing that Vg = 120V find the current (Rtot = (r3 + r4) / / r2 + r3 Itot and I find the current divider are the other or use Millman )

Fig.2: Knowing that Vg = 220V find the current (use Millman)

Fig.3: Knowing that Vg = 220V find the current (r = (r5 + r6) / / r2 and then use Millman)

4: Knowing that Vg = 120V 2A and find the current Ig = (Millman)

5: Knowing that Vg = 120V find the current (r = r2 + r5 / / (r3 + r4) and Millman)

Fig.6: Knowing that VG1 = 120V, 130V and VG4 = Ig = 3A find Current

7: Knowing Vg = Ig = 120V and 1A find the current

Fig.8: Knowing that VG4 = VG1 = 120V and 100V find the current

9: Knowing and Vg2 VG1 = 100V = 50V find the current

Fig.10: Knowing and Ig = VG1 = 100V 4A find the current



AC

NB component values \u200b\u200band frequency can be chosen at will.


For all eleven circuits, Vi = 120V and the currents are determined in the various branches.

NB The procedure must be sgeuente:

1) Sketch the physical circuit

2) Calculate the reactance

3) Draw the circuit symbol with the impedance (complex numbers)

4) Determine the voltage and current (complex numbers)

Transfer functions

Fdt1: Calculate literally the parallel between a capacitor and a resistance

Fdt2: Calculate literally series between a capacitor and a resistance

Fdt3: Calculate the expression literally: z1 / / z2 + z3 = 1/Cs where z1, z2 and z3 = R = R + Ls

Fdt4: Calculate the expression literally: z1 + z2 / / z3 = 1/Cs where z1, z2 and z3 = R + Ls = R

Fdt5: Calculate the expression literally: (z1 + z2) / / z3 = 1/Cs where z1, z2 and z3 = R + Ls = R

Fdt6: Calculate the expression literally: z1 / (z1 + z2) where z1 and z2 = 1/Cs = R + Ls

Fdt7: Calculate literally the expression 1 / (+ 1/z1 1/z2) where z1 and z2 = 1/Cs = R + Ls

Fdt8: Calculate literally the expression: (1/z2) / (+ 1/z1 1/z2) where z1 and z2 = 1/Cs = R + Ls

NB

To determine the frequency response through the FDT is necessary: \u200b\u200b1

) Draw the physical circuit

2) Draw the circuit symbol in s (complex frequency)

3) Calculate Vo date Vg

4) Calculate A (s) = Vo / Vg

5) By calculating sine wave A ( jw) in magnitude and phase

6) Replace the numeric values \u200b\u200b(R, L and C)

7) plotted by varying the value of w from zero onwards

Fdt9: For all eleven circuits figure should be determined in the function Transfer Vu / Vi in literal form

Bode amplitude


Bode1:

Draw the function A (s) = [s +1000.1 s ^ 2 +100] / [(s + 1) (s +10000)]

Draw the function A (s) = [1000s +100] / [(s +1) (s +10000)]

Draw the function A (s) = s [1000s + 100] / [(s +1) (s +10000)]

Draw the function A (s) = s [1000s +1] / [(50s +1) (5s +10000)]

the A Draw (s) = [s ^ 2 +100 s +10000] / [(s +1) (s +10000)]

Draw the function A (s) = [s ^ 2 +100 s +10000] / [s ^ 2 +500 s +100]


BJT using the polarization characteristics





















This is the characteristic input





















This is the output characteristic

1) Draw the circuit biasing BJT with two generators (Vcc = 12V, Vbb = 1.5 V) and two resistance (Rb = 100K, Rc = 2K) and using the two features in the figure to find the resting point of entry (IBQ, Vbeq) and output (ICQ, Vceq)

Procedure: Plot the input load (pass for Vbb / Vbb and Rb) and output (pass for DC / DC and RC) are the points of intersection are the values.

2) Repeat the same exercise only doubling Rb

3) Repeat doubling Rc

4) Add Re = 0.33K

procedure: the only point where they pass through the lines (Vcc / (Rc + Re) and Vbb / (Rb + BRE)). The problem is to calculate the B and that you are looking for a mid-point in the output characteristics and calculating the ratio Icq / IBQ

5) Repeat with Rb = 10K, Re = 0K and say if the BJT is in saturation.

6) Repeat with Rc = 10K, Re = 0K and say if the BJT is in saturation.

7) Repeat with Rb = 10K, Re = 0.56K and say if the BJT is in saturation.

8) Repeat with Rc = 10K, Re = 0.22K and say if the BJT is in saturation.


BJT polarization without the use of characteristics and with the sole knowledge of hFE or beta using a circuit with two resistors.

It is suggested that you use a circuit with Vbb, Vcc, Rb and Rc and the value of beta = 200.

For the verification part of the Vbb, Vcc, Rc and Rb and the process the council is this:

assumed in the BJT region Ib active
calculation equation of the mesh input
calculating the beta Ic Vce
calculation equation of the mesh output
condition occurs if the active region

occurred hypothesize the saturation region

calculation Ib equation mesh input
Ic calculation equation of the mesh output
condition occurs saturation region

1) Vbb = 2V, Vcc = 15V, Rc and Rb = 47K = 1K

2) Vbb = 3V, Vcc = 15V, Rb = Rc = 2.2K and 47K

3) Vbb = 1V, Vcc = 15V, Rb = Rc = 2.2K and 47K

4) Vbb = 3V, Vcc = 15V, Rc = 4.7 K and Rb = 68K

for the project from Ic, Ib (Or beta), Vbe, Vce, Vbb, Vcc and this procedure is recommended:

calculation of the equation Rb mesh input
calculation of the equation Rc Mesh
found out the commercial value is passed to verification of the rest point by calculating
Ib Vbe, Vce and Ic

1) Vbb = 2V, Vcc = 15V, Ib = 15ua, Ic = 2mA, Vce = 6V, Vbe = 0.7V

2) Vbb = 3V, Vcc = 12V, Ib = 25uA, IC = 3mA, Vce = 8V, Vbe = 0.7V

3) Vbb = 2V, Vcc = 10V, Ib = 45ua, Ic = 3mA, VCE = 2V, Vbe = 0.7V

4) Vbb = 2V, Vcc = 10V, Ib = 25uA, IC = 2mA, Vce = 4V, Vbe = 0.7V


polarization without the use of the BJT features and with only the knowledge of hFE or beta using a circuit with 3 resistors.


polrizzazione In the circuit with three resistors of the procedure is similar
only changing the loop equations and the project must be added the possibility of project
Re Ic is about 10% of Vcc.

Check or analysis


1) Vbb = 2V, Vcc = 15V, 1K = Rc, Re and Rb = 47K = 0.33K

2) Vbb = 3V, Vcc = 15V, Rc = 2.2K, D = 0.27 K and Rb = 47K

3) Vbb = 1V, Vcc = 15V, Rc = 2.2K, D = 0.68K and Rb = 47K

4) Vbb = 3V, Vcc = 15V, Rc = 4.7K, D = 0.56 K and Rb = 68K


Project:

1) Vbb = 2V, Vcc = 15V, Ib = 15ua, Ic = 2mA, Vce = 6V, Vbe = 0.7V

2) Vbb = 3V, Vcc = 12V, Ib = 25uA, IC = 3mA, Vce = 8V, Vbe = 0.7V

3) Vbb = 2V, Vcc = 10V, Ib = 45ua, Ic = 3mA, VCE = 2V, Vbe = 0.7V

4) Vbb = 2V, Vcc = 10V, Ib = 25uA, IC = 2mA, Vce = 4V, Vbe = 0.7V



BJT polarization without the use of characteristics and with the sole knowledge of hFE or beta using a circuit with 4 resistors.


In polrizzazione circuit with four resistors
a similar process is only changing the loop equations and the project must be added
the idea of \u200b\u200bthe value of the divider input.

Verification or analysis


1) Vcc = 15V, Rc = 1K, Re = 0.33K, R1 = 47K and R2 = 5.6K

2) Vcc = 15V, Rc = 2.2K, D = 0.27K, R1 = 33K and R2 = 6.8K

3) Vcc = 18V, Rc = 2.2K, D = 0.68K, R1 = 33K and R2 = 8.2K

4) Vcc = 18V, Rc = 4.7K, D = 0.56K, R1 = 33K and R2 = 6.8K


Project:

1) Vcc = 15V, Ib = 15ua, Ic = 2mA, Vce = 6V, Vbe = 0.7V

2) Vcc = 12V, Ib = 25uA, IC = 3mA, Vce = 8V, Vbe = 0.7V

3) Vcc = 10V, Ib = 45ua, Ic = 3mA, VCE = 2V, Vbe = 0.7V

4) Vcc = 10V, Ib = 25uA, IC = 2mA, Vce = 4V, Vbe = 0.7V


EC Amplifier

1) Draw a complete CE amplifier stage, calculate Ai, r'i, Av, Ri, Avs alpha and knowing that Rs = 1K, R1 = 47K, R2 = 5.6K, D = 0.39K, Rc = 2.2K, hie = 1K, hfe = 220, RL = 5k

2) Draw a complete CE amplifier stage, calculate Ai, r'i, Av, Ri, Avs alpha and knowing that Rs = 1K, R1 = 33K, R2 = 5.6K, D = 0.39K, Rc = 2.2K, hie = 1K, hfe = 220, RL = 5k

3) Draw a complete CE amplifier stage, calculate Ai, r'i, Av, Ri, Avs alpha and knowing that Rs = 1K , R1 = 47K, R2 = 6.8K, D = 0.39K, Rc = 2.2K, 2K = hie, hfe = 180, RL = 10k

4) Draw a complete CE amplifier stage, calculate Ai, r'i, Av , Ri, Avs alpha and knowing that Rs = 1K R1 = 47K, R2 = 5.6K, D = 0.68K, Rc = 4.7K, 2K = hie, and hfe = 200 RL = 5k

5) Draw a complete CE amplifier stage, calculate Ai, r'i, Av, Ri, Avs alpha and knowing that Rs = 1K, R1 = 33K, R2 = 5.6K, D = 0.56K, Rc = 3.9K, 1.5K = hie, hfe = 220, RL = 5k



Multistage

To solve the exercises you need:
1) Draw the complete multistage
2) To analyze the static part of each stage (draft or check)
3) Draw the dynamic circuit of each stage
4) Determine the transfer functions starting from 'last stage


Mult1:
EC + CC
You know the rest point CE (Ic = 3mA, VCE = 5V), while in DC should be determined with R3 = R4 = 33K = 1K and RE2. We know that Rs = 1K RL = 5.6K, hie = 1K, hfe = 220 (identical in both stages)

Mult2:
EC + DC
You know the rest point of EC (Ic = 3mA, VCE = 5V ) as necessary to define, DC = 33K R3 = R4 = 1K and RE2. We know that Rs = 1K RL = 5.6K, hie = 1K, hfe = 220 (identical in both stages) and the output is the collector.

Mult3:
EC + DC
You know the rest point of EC (Ic = 3mA, VCE = 5V), while in DC should be determined with R3 = R4 = 33K = 1K and RE2. We know that Rs = 1K RL = 5.6K, hie = 1K, hfe = 220 (identical in both stages) and the output is nell'emettitore.

Op

1) Designing a reversing OA to amplify -5

2) Draw a noninverting OA to amplify 3

3) Design an adder inverting -5 to amplify two signals of amplitude 0.1 V and 0.15 V entry to

4) Draw a sottratore that makes a difference of two signals of amplitude 1 V and 0.55 V at places

5) Draw a non-inverting adder 2 to amplify the two signals of amplitude 0.1 V and 0.15 V entry to

6) Draw an open loop comparator with OA and the output obtained by placing two input signals sinusiodali with the same frequency but phase and amplitude of 2V and 5V

7) Draw the circuit of a Schmitt trigger with OA and the output obtained by placing two input signals sinusiodali with the same phase and frequency but amplitude 2V and 5V

Operational and filters

In circuits with OA:

• z1 connects the generator or the mass with the inverting terminal
  
• z2 connects the inverting output terminal
• z3 connects the generator or the mass with the non-inverting terminal
  
• z4 connecting the mass with the non-inverting terminal

1. Given an inverting amplifier with z1 and z2 = 10R = R +1 / (Cs) Av calculate and draw its graph with Bode knowing that R = 1K and C = 10nF
2. Given an inverting amplifier with z1 = R +1 / (Cs) and z2 = 10R +1 / (Cs) Av calculate and draw its graph with Bode knowing that R = 1K and C = 10nF
3. Given an inverting amplifier with z1 and z2 = R + Ls = 10R +1 / (Cs) Av calculate and draw its graph with Bode knowing that R = 1K, L = 10mH and C = 10nF
4. Given an inverting amplifier with z1 and z2 = R = 9R / / (R +1 / (Cs)) Av calculate and draw its graph with Bode knowing that R = 1K and C = 10nF
5. Given a non-inverting amplifier with R = z1, z2 = 10R, = R z3 and z4 = 1 / (Cs) Av calculate and draw its graph with Bode knowing that R = 1K and C = 10nF
6. Given a non-inverting amplifier with R = z1, z2 = 10R, z3 = 1 / (Cs) and z4 = R Av calculate and draw its graph with Bode knowing that R = 1K and C = 10nF

Drambuie What Is Nice To Mix With Drambuie?

Exercises for Class 5 °

In the previous figure are shown the circuits where you have to find the fdt Vo / Vi

1-2-3) Procedure: Use the voltage divider setting the numerator of the impedance which pick up the output voltage and the denominator the sum of the impedances of the circuit

4-5-6-7-8-9) Method: Using Millmann or after taking the parallel impedance output I'm a divider

10-11) Method: Using Millmann to calculate the tension between the core and the mass then use the divider to determine the output voltage

RNTS1:

NB

Apply sequence of operations shown in Figure

Knowing Ri = 20K, Re = 0.56K, Rf = 33K, Avo = 800, Ro = RL = 4.7K and 5.6K determine aVF, Rof and Rif

and verify that AVF is close to the value 1/beta

Knowing Ri = 20K, Re = 1.2K, Rf = 33K, Avo = 800, fl = 450Hz, fh = 300KHz, Ro = RL = 4.7K and 5.6K determine aVF, FLF, fhf, Rof and Rif and verify that AvF nears a 1/beta

Knowing Ri = 20K, Re = 1.2K, Rf = 33K, Avo = 800, fl = 450Hz, fh = 300KHz, Ro = 4.7K and determining RL = 5.6K aVF, FLF, fhf, Rof and Rif and verify that AvF nears a 1/beta

Osc1:

Draw a Wien bridge oscillator that oscillates at 5kHz. The capacitors have a value of 22nF and R that connects the inverting terminal to ground is 2.2K. Determine the values \u200b\u200bof other R.


Draw a Wien bridge oscillator, knowing that C = 10nF and R = 4.7K, while the R that connects the output to the inverting terminal is 6.8K. Finding the oscillation frequency and the other R.

Method: Simply open the ring on the operational +, calculate and A beta in literal form using the complex frequency s, set aside the real part of the denominator of the beta so that beta becomes real and its reciprocal is calculated the value of A and then the resistance values.

Osc2:

In opening the ring oscillator is estimated that the beta is given by the expression 2RCS / [(RCS) RCS +6 ^ 2 + 3] with C = 10nF and R = 2.2K. Finding the oscillation frequency and the minimum value of A necessary for its operation

Procedure: w to simply cancel the real part of the denominator of beta and, once made, should be reversed to find

Osc4: Given a Colpitts oscillator in where the amplification is -8 C and output swings 100Khz 2nF knowing that determine the value of L and the input capacitor.

Osc5: Given a Hartley oscillator where L1 = L2 = 2.2uH 1UH and find the frequency of oscillation and amplification, knowing that the value of C = 100pF

Procedure: we always here from the theorem of the three points, writing the expressions of the impedance is calculated by writing we are beta then calculates A.

Osc6: Given a phase shift oscillator in which C = 10nF and R = 2.2K find the minimum amplification and oscillation frequency.

Procedure: beta = (RCS) ^ 3 / [(RCS) ^ 3 +6 (RCS) RCS ^ 2 +5 +1] for which cancels the real part of the denominator we find for inverting the value of beta is

Osc7: Designing with NE555 astable where f = 4 kHz and the DC is 60%

Procedure: Based on the scheme chosen are the time constants of charging and discharging, with these are the times when the pulse remains high and low.

Osc7: Repeat with DC 25%

Osc8: Design an astable with OA so that f = 5kHz and the DC is 50% at Vcc = 18V.

Procedure: Based on the scheme chosen are the time constants of charging and discharging, with these are the times when the momentum is high and low.

Osc9: Repeat with DC 25% and 70%

Osc10: Design a monostable with OA, complete control circuit, which produces an output pulse of 3ms, with Vcc = 18V. Also means the minimum value of the square wave frequency used for switching.

Osc11: Design a monostable with NE555, complete control circuit, which produces an output pulse of 3ms. Also means the minimum value of the square wave frequency used for switching.

Osc12: Design a triangular wave generator that produces a maximum voltage of 10V at a frequency of 3 KHz with Vcc = 18V.


For the filters we must remember the formulas from which to obtain the design parameters:

Low pass:

A (s) = Ao / [(s ^ 2 / w ^ 2) +2 z (s / w) + 1] (fdt general)

A (s) = K / [(RCS) ^ 2 + (3-k) +1 RCS] with K = 1 + Ra / Rb (FDT specification filter VCVS)

High Pass :

A (s) = Ao (s / w) ^ 2 / [(s ^ 2 / w ^ 2) +2 z (s / w) +1]

A (s) = K (RCS) ^ 2 / [(RCS) ^ 2 + (3-k) +1 RCS] with K = 1 + Ra / Rb


Band Pass:

A (s) = 2zAo (s / w) / [(s ^ 2 / w ^ 2) +2 z (s / w) +1]

A (s) = K (RCS) / [(RCS) ^ 2 + (4-k) +2 RCS] with K = 1 + Ra / Rb


NB The values \u200b\u200bof z F necessary for the projects are located in tables in the book

The way to proceed in doing the exercises when designing a filter is this:

1) schematic contrasseganto the names of the components to be determined
2) to determine the relationship between filter parameters (w, z, Ao) and the values \u200b\u200bof circuit components (the various R and C circuit) from the comparison between the FDT general and specific circuit
3) if necessary to find values \u200b\u200bin the table design of the filter (F z) and so the natural fo
4) calculate the R and C of the circuit design


Filtr1: Designing a filter of the first order low-pass amplification of 3 and ft = 2 KHz

Filtr2: Designing a filter of the first order high-pass amplification of 2.5 and ft = 5kHz

Filtr3: Designing a filter of the first order high-pass amplification of 4dB and ft = 1KHz


Filtr4: Design a second order filter of the second lowpass Butterwotrh and ft = 5kHz

Filtr5: Design a second order filter of the second lowpass Butterwotrh with amplification and ft = 5dB 3KHz

Filtr6: Design a second order filter of the second highpass Butterwotrh amplification of 2.5 and ft = 4KHz

Filtr7: Designing a filter of the II order lowpass Chebyshev with ft = 4KHz

Filtr8: Design a filter II order highpass Chebyshev with ft = 3KHz

Filtr9: Design a second order filter of the second highpass Chebyshev with ft = 3 KHz and gain 6dB

Filtr10: Designing a filter of the II order lowpass Bessel ft = 3 KHz

Filtr11: Designing a filter of the II order lowpass Bessel ft = 3 KHz with a gain of 8dB

Filtr12: Designing a filter of the third order lowpass Butterworth ft = 3 KHz 4dB gain and

Filtr13: Designing a filter of the third order highpass Butterworth ft = 4 kHz and gain 4dB

Filtr14: Designing a filter of the third order lowpass Chebyshev with ft = 4 kHz and gain 4dB

Filtr15 : Designing a filter of the third order highpass Bessel ft = 4 kHz and gain 4dB



Filtr20: Design a bandpass filter (narrow band) for = 4 kHz and gain 4dB

Filtr21: Design a bandpass filter ( narrowband) for = 4 kHz and Q = 5

Filtr22: Design a bandpass filter (narrow band) and for = 5kHz bandwidth of 2 kHz

Filtr23: Design a two-stage bandpass filter (bandwidth close) with for = 4kHz and Q = 5



Filtr30: Design a bandpass filter in broadband (the II order) with fl = fh = 12KHz and 1KHz

Filtr31: Design a bandpass filter in broadband (the II order) in two stages with fl = 1kHz and 12kHz bandwidth


Filtr40: Designing an Exclude filter bandwidth (narrow band) with for = Q = 3 and 3Khz

Filtr41: Designing an Exclude filter bandwidth (in narrowband) with B = for = 5kHz 2kHz

Filtr42: Designing an Exclude filter bandwidth (high bandwidth) with fl = B = 1kHz and 10kHz

Filtr43: Designing an Exclude filter bandwidth (high bandwidth) with fl = fh = 1kHz and 11kHz

to Remember power, the following definitions disting the static variables from those dynamics: CCP, PD, PL, Vceq, Icq, Pu, F, age, or THD Dtot, Icm, Vcem, VLM and ILM

The exercises are performed using the stylized graphic technical prescriptions of the output to identify the location of the rest.

Once you have determined the point of rest diseganrela static and dynamic load line, and then determine the value vcem that the point of rest are discussing cuts without distortion or

POT1: Find the rest point of a BJT which supplies a load Rc current path from Vcc = 12V, Rc = 8 Ohm, Beta = 40, RB = 0.5K and the maximum value for the oscillation whereas Vcesat = 0V. Also calculate PD, PL, F and age.

POT2: Find the rest point of a BJT which supplies a load current flowing Rc with Vcc = 15V, Rc = 8 Ohm, Beta = 50, RB = 0.82K, and the maximum value for the oscillation whereas Vcesat = 1.5 V. Also calculate PD, PL, F and age.

Pot3: Find the rest point of a BJT which supplies a load current flowing Rc with Vcc = 15V, 8 Ohm = Rc, Re = 1ohm, Beta = 80, RB = 0.56K, and the maximum value for the oscillation Whereas Vcesat = 1V. Also calculate PD, PL, F and age.

Pot4: Find the rest point of a BJT which supplies a load current flowing Rc with Vcc = 15V, Rc = 4 Ohm, Re = 2Ohm, Beta = 80, RB = 0.56K, and the maximum value for the oscillation Whereas Vcesat = 1V. Also calculate PD, PL, F and age.

Pot5: Find the rest point of a BJT feeding an RL load current path from Vcc = 15V, RL = 4 Ohm, Re = 0Ohm, Beta = 80, RB = 0.56K, and the maximum value for the ' Whereas oscillation Vcesat = 0V. Also calculate PD, PL, F and age.

Pot6: Find the rest point of a BJT feeding an RL load current path from Vcc = 15V, RL = 4 Ohm, Re = 2Ohm, Beta = 80, RB = 0.56K, and the maximum value for the ' Whereas oscillation Vcesat = 1V. Also calculate PD, PL, F and age.

Pot10: Find the rest point of a BJT feeding an RL load with a transformer coupled with Vcc = 15V, RL = 4 Ohm, n = 2, Beta = 80, RB = 0.56K and maximum value for the oscillation whereas Vcesat = 1V. Also calculate PD, PL, F and age.

Pot11: Find the rest point of a BJT feeding an RL load with a transformer coupled with Vcc = 15V, RL = 8 Ohms, n = 3.2, Re = 2Ohm, Beta = 80, RB = 0.56K and value whereas the maximum oscillation Vcesat = 1V. Also calculate PD, PL, F and age.